The present invention relates to a method of via filling. More specifically, it relates to a via filling method that provides superior filling properties and superior planarization as compared to conventional methods.
There have been strong demands in recent years for thinner printed wiring boards with higher interconnect densities compatible with improved functionality and miniaturization of electronic equipment such as personal computers. One method by which to respond to these demands has been to use multilayer printed wiring boards (xe2x80x9cbuild-upxe2x80x9d printed wiring boards) that are manufactured using a build-up process technology wherein each individual layer is patterned as it is layered on the printed wiring board.
In recent years, a method known as xe2x80x9cvia fillingxe2x80x9d has been developed wherein micro via holes (hereinafter termed xe2x80x9cMVHsxe2x80x9d in some cases) are entirely filled with conductive material to provide electrical conductivity between adjacent layers of a build-up printed wiring board. Such via filling makes it possible to increase the effective area of printed wiring boards by obtaining adequate electrical conductivity using MVHs with smaller diameters than those that can be used with the conventional method of plating only the inner wall surfaces of the MVHs. This method effectively reduces the size of the printed wiring boards and increases the density thereof.
Various via filling methods have been described, including a method where the MVHs are filled with electrically conductive paste using a printing method, a method where only the conductive layer at the bottom of the MVH is activated and non-electrolytic plating is layered selectively thereon, and a method where electrolytic plating is performed.
However, the conductivity of conductive pastes is low compared to pure metal because the pastes are mixtures of metal and organic materials, making it difficult to achieve adequate electrical conductivity in small-diameter MVHs. Thus, the electrically conductive paste cannot be said to be an effective way to miniaturize, and increase the density of, printed wiring boards. In addition, filling that is done using a printing method requires viscous paste to be filled into small diameter holes that are closed on one end; however, because the paste is viscous, it is difficult to fill the entire hole without leaving voids. While the method that uses non-electrolytic plating is superior to the electrically conductive paste method in that the MVH fill material is a high-conductivity metal deposit, the speed at which the plating layer is deposited is slow, causing problems with productivity. For example, when a typical high-speed non-electrolytic copper plating solution is used, the deposition rate of the plating film is about 3 microns per hour. When such method is used to fill with copper plating a typical blind via hole (termed xe2x80x9cBVHxe2x80x9d in some cases below) with a diameter of 100 xcexcm and a depth of 100 xcexcm, the productivity is extremely bad, with the process taking more than 30 hours.
Because electrolytic plating can reduce the plating time substantially when compared to non-electrolytic plating, there have been high hopes for the application of electrolytic plating to MVHs. However, when metal is deposited on all surfaces within the MVH, the deposition rate in the vicinity of the bottom surface inside the MVH must be faster than the deposition rate near the opening if the inside of the MVH is to be filled with metal without leaving voids. When the deposition rate near the bottom surface is the same as or slower than the deposition rate at the opening, the MVH either will not be filled, or the opening part of the MVH will become blocked before the inside of the MVH is completely filled with metal, causing voids inside the MVH, with results being inadequate for practical use in either case. Consequently, successfully filling the micro via holes requires strict control of the filling parameters so as to be able to deposit the metal appropriately.
Conventionally, a direct current typically has been used in the electrolysis when using an electrolytic plating solution to expedite the deposition rate in the vicinity of the bottom surface of the MVH. While a method where PR (periodic reverse) electrolysis, wherein the anode and cathode are alternated, is already known, the cycle time has been extremely long, ranging from several seconds to several tens of seconds, so the metal deposition rate has not been satisfactorily slow.
Furthermore, the surface that has been filled has not been flat, but rather the center of the via has had a dimpled shape. Because of this, when the filling was extended to an adequate height, the plating on the parts outside of the via holes would be thicker, which was undesirable not only because this caused a host of problems in subsequent processing, but also undesirable from an economic perspective.
Unexamined Japanese Patent Application Publication 2000-68651 discloses a method for performing electrolytic plating using a PPR (Pulse Period Reverse) electric current and a solution containing specific compounds containing sulfur atoms. The invention disclosed in this Application controlled the deposition and removal of a specific sulfur-containing compound to and from a substrate through the use of a PPR current; however, successful filling high-aspect-ratio micro via holes would require even more stringent control of the plating conditions.
The present invention is the result of reflection on the facts described above, and its object is to provide a novel filling method that provides superior filling properties in a short period of time while providing a surface with superior planarization.
The present invention provides a via filling method wherein a PPR electric current is applied with a cycle having a forward electrolysis interval of 1 to 50 msec and a reverse electrolysis interval of 0.2 to 5 msec, with an F/R ratio in the range of 1/1 to 1/10. The F/R ratio is the ratio of the forward electrolysis current density to the reverse electrolysis current density. Accordingly, the present invention provides a method of filling vias on a substrate comprising contacting the substrate with a metal electroplating bath and applying sufficient current density to deposit a desired metal layer, wherein the current density is applied in a cycle of a forward current density (F) for 1 to 50 msec, and a reverse current density (R) for 0.2 to 5 msec, where a ratio of F/R is from 1/1 to 1/10.
Also provided by the present invention is a method of filling vias on a substrate comprising contacting the substrate with a metal electroplating bath and applying sufficient current density to deposit a desired metal layer, wherein the current density is applied in a first cycle of a first forward current density (F1) for 1 to 50 msec and a first reverse current density (R1) for 0.2 to 5 msec, where a ratio of F/R is from 1/1 to 1/10, and a second cycle of a second forward current density (F2) for 1 to 50 msec and a second reverse current density (R2) for 0.2 to 5 msec where a ratio of F2/R2 is from 1/1 to 1/0.1, where the second reverse current density is less than the first reverse current density.